1. Field of the Invention
The present invention relates to a method of fabricating a fin field effect transistor (FinFET). More particularly, the present invention relates to a method of fabricating a fin field effect transistor (FinFET) having a plurality of vertically protruding channels in a semiconductor substrate.
2. Description of the Related Art
In order to improve the performance and reduce the fabrication cost of semiconductor devices, the integration density of semiconductor devices continues to increase. Increasing the integration density of semiconductor devices requires the development of techniques for reducing the feature size of semiconductor devices.
In conventional semiconductor fabricating processes, the channel length of a metal-oxide-semiconductor field effect transistor (MOSFET) is decreased to improve the operating speed and integration density of a semiconductor device. Such decrease in the channel length, however, may degrade the operational characteristics and effectiveness of the device as an active switch. For example, as the distance between the source and the drain is further reduced, a phenomenon referred to as the short channel effect can occur. Thus, it becomes difficult to effectively suppress the influence of the electrical potential of the drain on the electrical potentials of the source and channel. However, since a conventional MOSFET, in which a channel is disposed parallel to the upper surface of the semiconductor substrate, is a planar channel device, it is difficult to not only structurally scale down the device area consumed by the MOSFET, but also to suppress the occurrence of the short channel effect.
A FinFET has a structure in which a fin-shaped, three-dimensional active region is formed, and both lateral side surfaces and a top surface of the fin-shaped active region are surrounded by a gate. Thus, the FinFET includes a vertically oriented channel, rather than a planar channel. Unlike a planar MOSFET, since the FinFET includes a vertical channel that is disposed on a substrate, the size of the FinFET can be more readily scaled down, and the short channel effect can be mitigated by greatly reducing the junction capacitance of the drain. In addition, the FinFET offers other superior electrical properties such as higher drive current and lower leakage current induced by an improved sub-threshold current and reduced drain induced barrier lowering (DIBL). Accordingly, in view of these advantages of the FinFET, extensive research into replacing conventional MOSFETs with FinFETs has recently been conducted.
FinFET structures are described in U.S. Pat. No. 6,391,782 by Yu et al. entitled “Process for forming multiple active lines and gate-all-around MOSFET”, U.S. Pat. No. 6,562,665 by Yu et al. entitled “Fabrication of field effect transistor with a recess in a semiconductor pillar in SOI technology”, U.S. Pat. No. 6,642,090 by Fried et al. entitled “Fin FET device from bulk semiconductor and method for forming, and U.S. Pat. No. 6,664,582 by Fried et al. entitled “Fin memory cell and method of fabrication”, each being incorporated herein by reference.
Although the FinFET offers these superior electrical characteristics, it is currently difficult to fabricate a FinFET having a very short and uniform channel width, e.g., less than 30 nm, because of the limitations of current lithography techniques. Such lithography-related limitations also lead to other disadvantages. For example, if the fin structures are not formed to a uniform width, current dispersion characteristics may be adversely affected. Also, to form a three-dimensional FinFET channel on a substrate, a photolithography process must be performed. However, the critical line width that can be obtained by the photolithography process is limited. Therefore, an improved method for forming a three-dimensional channel having a fine line width below the resolution limit of the photolithography process is required.